The present invention is related to electronic signal conversion, and more particularly to pipelined analog to digital converters.
Pipelined analog to digital converters are one of the most popular analog to digital conversion architectures for medium to high speed conversions. One of the trends in the art has been to decrease the number of bits per stage in the pipeline to reduce any gain-bandwidth requirements of the pipeline residue amplifiers. However, fewer bits per stage increases the number of stages required for a given resolution. In addition, a more serious drawback is that fewer bits per stage increases the sensitivity to component matching errors.
Further, previous multi-bit-per-stage pipelined ADC sub-stages use a larger number of comparators than that required for the desired gain. Depending on the number of comparators and the sampling capacitors, either a decoder is inserted between the comparators and the switches in the Multiplying Digital-to-Analog Converters (MDACs) or a large number of capacitors units are used in the MDAC. The decoder introduces delay and the large number of capacitor units worsens the matching, increases the routing parasitics, and even reduces the feedback factor sometimes. All of these require faster residue amplifiers and leads to less linear analog to digital converters.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems, circuits and methods for electronic signal conversion.